Periodic signals, also known as clock signals, are well known and widely utilized in both digital and analog circuits for a variety of functions. Periodic signals may be derived from a component generating a reference signal, such as a crystal oscillator, from a variable circuit such as a Voltage Controlled Oscillator (VCO), and from other sources. In many cases, particularly in Radio Frequency (RF) circuits, it is advantageous, if not critical, for such periodic cycles to have a carefully controlled and maintained duty-cycle. The duty-cycle for a periodic signal is an indication of the amount of a period that the signal is in one state or phase (e.g., high) vs. the other state or phase (e.g., low). For example, a 75% duty-cycle periodic signal is high for 75% of the period, and low for only 25% of the period.
One important and very common subset of periodic signals are those having a 50% duty-cycle. That is, for substantially half of the period, such a signal should be at a high level or state (i.e., above a predetermined transition voltage, such as midway between its peak-to-peak voltage swing), and for substantially half of the period, the signal should be at a low level or state. The 50% duty-cycle is common for clock signals in digital circuits. Among other factors, a 50% duty-cycle ensures that circuit logic and other components imposing a propagation delay have equal time to process signals in both phases, or states, of the periodic signal.
In some applications, a precisely-controlled, but non-50%, duty-cycle is desirable. Examples include LO signals for harmonic mixers, and mixers with lower second-order distortion. In these applications, a non-50%, duty-cycle periodic signal may vary from an initial duty-cycle
In real-world designs, periodic signals vary from a their initial duty-cycle (whether 50% or some other duty-cycle value) for a variety of reasons.
One source of duty-cycle skew in 50% duty-cycle periodic signals is a fractional divider, also referred to as a fractional-N clock divider, which is utilized extensively in communication systems. A fractional divider divides a periodic RF signal by a non-integer division ratio, generating a new periodic signal having a lower frequency and a non-50% duty-cycle.
Other sources of duty-cycle skew, affecting all periodic signals, include clock signal amplification and distribution circuits. For example, many RF circuit components exhibit different propagation delays for high and low signal phases or transitions, and such imbalances may add to alter the overall duty-cycle of a periodic RF signal. Accordingly, the duty-cycle of a periodic signal may need to be corrected to bring it closer to a desired duty-cycle.
Duty-cycle correction circuits are known in the art, particularly for correcting 50% duty-cycle signals. In most cases, prior art circuits used for correcting duty-cycle perform three functions. First, the non-symmetrical (i.e., non-50% duty-cycle) periodic signal is delayed. Second, a mathematical (i.e., logical) expression (e.g., AND/OR) is applied between the non-symmetrical periodic signal and the delayed signal. Third, a correction is applied to one signal or the other, or both, to construct a new periodic signal having an accurate 50% duty-cycle. The correction can be made with a feedback loop or a calibration algorithm.
Such prior art duty-cycle correction circuits exhibit a number of deficiencies. They are electronically noisy, because the newly constructed signal is built, at least partly, from a delayed periodic signal. By delaying the rise and fall times, the signal uncertainty increases, which increases the phase noise. The prior art circuits are also sensitive to process spread and environmental changes, such as temperature variation.
Many RF functions are implemented using a balanced circuit architecture, in which positive and negative components of a signal are processed in complimentary, or mirrored, circuit components. Balanced circuits inherently reject common-mode noise. However, the common-mode noise rejection of balanced circuits depends on closely matching complementary circuit components. It is difficult to build a fully balanced duty-cycle correction circuit according to prior art techniques, so that the corrected signal(s) have a proper balancing and accurate duty-cycle.
Finally, prior art duty-cycle correction methods require extra circuits, and hence silicon real estate, (e.g., in a feedback loop or for calibration). This not only leads to larger integrated circuits, but also increases power consumption. Many modern RF devices are portable and operate on batteries, and hence reducing power consumption is an important design goal.